(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the use of thin silicon oxynitride layers to shield select portions of MOSFET device structures against etchants.
(2) Description of Prior Art
The fabrication of integrated circuit chips comprises the formation of semiconductor devices within the surface of a single crystalline silicon wafer. The semiconductive elements of metal-oxide-silicon-field-effect-transistors (MOSFETs) are contained within the surface of the single crystalline substrate wafer and are formed by ion-implantation using the control electrode, a polysilicon gate formed over the substrate, as an implantation mask. The source and drain regions of the MOSFET are thereby self-aligned to the gate electrode.
Many variations of this principle of self alignment to the polysilicon gate have been developed to improve device performance and stability, in particular, the use of side walls on the edges of the polysilicon gate have permitted the tailoring of source and drain diffusions at the ends of the channel region to control short channel effects. These advances in MOSFET processing have resulted in high performance sub-micron sized devices of many types. The lightly-doped-drain (LDD) structure, used universally in sub-micron MOSFET technology, is a notable example of this side-wall tailoring.
The use of insulative sidewalls and caps over polysilicon conductors has also permitted the formation of self-aligned contacts to MOSFET active elements. Self-alignment processing utilizes reactive-ion-etching (RIE) to anisotropically etch vertical walled openings, typically through insulative layers, such as silicon oxide and various silicate glasses.
Self-aligned-contacts can be made in various configurations. Typically an insulative sidewall is provided along the edge of the polysilicon gate electrode. The sidewall provides an insulative spacing between the contact and the polysilicon gate. A metal such as platinum or titanium is deposited over the wafer. Annealing causes the metal to react with the exposed silicon forming a silicide contact. Afterwards, un-reacted metal is etched away leaving the silicide which is then connected to metallization. This is known as the salicide process and is discussed in detail by Wolf, S., "Silicon Processing for the VLSI Era", Vol. 2, Lattice Press, Sunset Beach, Calif., (1990),p143ff.
After a salicide contact is formed an insulative layer is deposited and openings are etched to access the contact. In very dense geometries the sidewalls assist in maintaining sufficient insulative spacing between the source/drain contact and the polysilicon gate. However, mis-alignment of the contact mask can lead to penetration of insulative material over the gate electrode leading to shorts bridging between the gate electrode and the source/drain.
FIG. 1 and FIG. 2 illustrate the formation of a contact opening to a source or drain of a polysilicon gate MOSFET with a contact mask mis-alignment using a conventional process. In FIG. 1 the cross section of a polysilicon gate 14 located over a gate oxide 12 on a wafer 10 is shown before the contact etch is performed. A cap oxide layer 18 is over the polysilicon and an inter-polysilicon-oxide layer (IPO) 20 has been deposited. A contact opening 26 defined by the mis-aligned photoresist mask 22 is to be made to access the active silicon area. The figures illustrates the contact opening 26 to be made between adjacent polysilicon gates although the structure to the right of the contact opening 26 could as well be field oxide isolation. The sidewalls 16, typically formed of silicon oxide, place the downward curvature of the IPO layer laterally away from the polysilicon element 14, thereby spacing the contact away from it. FIG. 2 shows the contact opening after the IPO layer has been etched by RIE. The mis-alignment of the photoresist mask results in penetration 27 of the cap oxide 18 posing a potential short. Additional sidewall portions 28 are formed which can be reduced only by over etching.
Su, et.al., U.S. Pat. No. 5,208,472 cites the use of dual spacers alongside the polysilicon gate electrode. the first spacer is used to define the source/drain implant and the second spaces a silicide contact further away from the gate electrode, thereby reducing gate-to-source/drain bridging. The spacers may be of silicon oxide or silicon nitride.
Lin, et.al., U.S. Pat. No. 5,286,667 cites the use of silicon nitride or silicon oxynitride to form an additional cap over the cap oxide 18. In addition, a thin layer of silicon nitride or oxynitride is used as an etch stop during the etching of a contact opening in a sacrificial borophosphosilicate glass (BPSG) layer. The etching is performed using both dry and wet etching. Although the isotropic wet etching undercuts the BPSG, this is of no consequence in Liu et.al.'s application since the remainder of this layer is subsequently removed.
In applications wherein the BPSG layer constitutes the IPO and the device geometries are in the sub-micron range, wet etching or isotropic dry etching is generally not permissible. Thus, substantial over etching by the RIE step may be required in order to properly remove the IPO within the contact opening. This requirement is best served by either forming the sidewall and polysilicon cap from a material having a high etch resistance to the RIE or by protecting them by a layer of such material. The material taught by this invention is a silicon oxynitride having a high silicon content. This material has a substantially superior etch resistance over silicon nitride and conventional silicon oxynitrides.
Tang et.al. U.S. Pat. No. 5,120,671 teaches a process for forming a self-aligned source region in a flash EEPROM (electrically-erasable-programmable-read-only-memory) device. A composite polysilicon stack is formed which comprises, not only conductive lines, but also storage elements of the EEPROM including an additional polysilicon layer and thin dielectric layers. The polysilicon stack is used to mask the etching of a field oxide region, resulting in a common self-aligned-source (SAS) unencumbered by field oxide encroachment. Liu U.S. Pat. No. 5,534,455 addresses the problem of silicon gouging and tunnel oxide undercutting by the SAS etch by performing the SAS etch after spacer formation. The spacer protects the edges of the polysilicon stack from attack by the SAS etch. The process taught by this invention provides comparable protection with less processing and is thereby more cost effective.